The invention relates to an integrated logic circuit, comprising a first sub-circuit which is arranged in a first path between a first power supply line, which carries a high supply voltage and an output of the circuit, and a second sub-circuit which is arranged in a second path between the output and a second power supply line which carries a low supply voltage, a current channel of at least one additional transistor being arranged in at least one of the paths in order to limit detrimentally strong electric fields in a further transistor of the sub-circuit in the relevant path.
A logic circuit of this kind is known from Netherlands Patent Application 8400523. In order to protect an N-channel field effect transistor in the second sub-circuit, arranged between an output junction point and the second power supply line carrying a low supply voltage, an additional N-channel field effect transistor is connected in cascode with the former transistor in the known logic circuit. The control electrode of the additional transistor is connected to the first power supply line carrying the high supply voltage. Thus, a voltage which is at most equal to the difference between the high and the low supply voltage, minus a threshold voltage of the additional transistor, will be present across the protected transistor. This reduces the risk of so-called hot carrier stress and hot carrier degradation caused by strong electric fields inside a transistor which are due to a high voltage across the transistor. As the dimensions o the transistors are smaller, these problems are more significant. When an N-channel field effect transistor in the first sub-circuit in a logic circuit is protected in the same way, the cascode connection of an additional N-channel field effect transistor gives rise to the problem that, when the first sub-circuit is conductive, a dissipating load connected to the outPut cannot be raised to a sufficientlY high logic level. This is because the two N-channel transistors are pinched increasingly further as the outPut voltage increases. Increasing the size of the transistors, therefore, does not make sense